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4.3.5.2 Super Mode (deprecated)

Note  Note

Super Mode is only available on adapter hardware version R2 001 V2 or R3 001 V0. This Mode is depecated.

  • The output Alarm signal (J3 pin 26) to the SP-ICE-3 Card will be activated whenever any of a user-specified set of patterns of active alarm inputs is recognised:

    • Alarm = alarm_pattern_A [ OR alarm_pattern_B [ OR ... ] ]

      • where

        alarm_pattern_X = alarm_input_J [ AND alarm_input_K [ AND ... ] ]

    • On the SP-ICE-3 Card the Alarm signal will cause the currently running job to be aborted.

  • The IPG-compatible Adapter allows connection of up to 6 alarm input signals.

  • The user can select which of the 26 = 64 possible patterns of alarm inputs will trigger the output Alarm signal to the SP-ICE-3 Card.

  • The 64 configuration bits for selecting the alarm input patterns are accessible as the Alarm Matrix via the IPG-compatible Adapter's SPI.

Configuration and Status Registers

The Configuration and Status Registers (CSR) for Super Mode are accessed indirectly via the SPI Register.

In oder to write a value to a CSR, the address of that CSR must be specified, along with the data to be written, via the SPI Register.

Similarly, in order to read from a CSR, its address must be specified via the SPI Register.

SPI Register Command/Data Bit Groups

Bit(s)

Command to SPI

Data from SPI

31

1 = WRITE access to the target CSR.

0 = READ access to the target CSR.

Unused: always 0.

30..24

Address of target CSR.

Unused: always 0.

23..16

Unused: always 0.

Unused: always 0.

15..0

WRITE access: Data to be written to the target CSR.

READ access: Data read from the target CSR.

CSR Details

Register Name

Address

Description

Unlock

0x00

A special unlock code sequence must be written to this CSR to enable WRITE access on all the other CSRs.

Note  Note

This sequence is not required for READ access to any of the CSRs.

The sequence requires writing the two data words 0xA569 and 0x1248 in that order to this CSR.

Writing any other value cancels the unlock sequence.

The state of the unlock sequence can be verified by reading the Unlock CSR:

  • A data value of 0x0000 means the write access to the other CSRs is disabled.

  • A data value of 0x0001 means the first unlock code word (0xA569) was written correctly.

  • A data value of 0x0003 means the unlock sequence is complete, and write access is enabled for all other CSRs.

Writing the first unlock code word (0xA569) to this CSR always leads to unlock state 0x0001.

  • Hence the unlocked state 0x0003 can be reached from any other (possibly unknown) state by entering the correct unlock code sequence.

Alarm Dead Time

0x01

This CSR specifies the minimum dwell-time (in microseconds) required for signals before they are recognised at the alarm inputs.

This feature is intended to suppress glitches on the alarm inputs.

The possible register values ranges from 0 to 1023. The recommended value is 2 (microseconds).

Interface Control

0x02

Some of the functions controlled by this CSR are also used in Universal Mode.

Configuration bits 15..12

Bit

Name

Description

15

DRIVER_ENABLE

Set to '1' to enable the digital output driver on the IPG-compatible Adapter.

If set to '0' the digital output signals on J1 are in tristate.

14

s5V_Enable

Set to '1' to enable the 5V on the IPG-compatible Adapter.

The 5V regulator supplies the Pull-Up resistors and the digital output drivers of J1.

13

VIO_Enable

Set to '1' to enable the VIO_out 5V voltage on J1 Pin 17.

The 5V regulator must be enabled by the s5V_Enable bit.

12

VIO_Port_Control

Set to '1' to enable PortD.4 to control the VIO_out 5V voltage on J1 Pin 17.

The 5V regulator must be enabled by the s5V_Enable bit.

Input Status

0x03

This register contains the status of the input signals to the IPG-comp Interface.

These bits have the exact same meaning as Status Bits 15..0 in Universal Mode.

Alarm Matrix

0x08,
0x09,
0x0A,
0x0B

This CSR contains 64 bits, spanning 4 addresses, from address 0x08 (bits 0..15) to address 0x0B (bits 48..63).

Each bit determines whether the output Alarm signal (to the SP-ICE-3 Card) will be activated for one particular combination of the 6 alarm inputs from the laser.

The alarm inputs are: Sync Alarm, Back Alarm, Alarm4, Alarm3, Alarm2, and Alarm1.

When the output Alarm signal is activated, the Yellow Alarm LED D10 on the bracket is switched ON (unless the shutter input J2 is open, in which case D10 blinks.)

FLA_Super_mode_Bitmap.svg not found.

Error LED Matrix

0x0C,
0x0D,
0x0E,
0x0F

This CSR contains 64 bits, spanning 4 addresses, from address 0x08 (bits 0..15) to address 0x0F (bits 48..63).

Each bit in the CSR determines whether the red Error LED should ON or OFF for one particular combination of the 6 alarm inputs from the laser.

The alarm inputs are: Sync Alarm, Back Alarm, Alarm4, Alarm3, Alarm2, and Alarm1.

LED D1 Matrix

0x10,
0x11,
0x12,
0x13

This CSR contains 64 bits, spanning 4 addresses, from address 0x10 (bits 0..15) to address 0x13 (bits 48..63).

Each bit in the CSR determines whether the Green LED D1 should be ON or OFF for one particular combination of the 6 alarm inputs from the laser.

The alarm inputs are: Sync Alarm, Back Alarm, Alarm4, Alarm3, Alarm2, and Alarm1.

Revision

0x7F

This CSR contains the revision number of the FPGA image.

Programmatic Configuration via SPI

The IPG-compatible Adapter's SPI can be used for configuration as demonstrated in the following example.

C#
Copy
using ( ClientAPI client = new ClientAPI( CardIP ) )
{
    try
    {
        // Get the current SPI configuration, and adjust
        // it to make sure that Module 0
        // is enabled with correct settings.
        SpiConfig sc = client.Sfio.Spi.GetConfig();
        sc.Modules[2].Enabled = true;
        sc.Modules[2].OutputSource = DataSource.Spi;
        sc.Modules[2].BitsPerWord = 32;
        sc.Modules[2].SpiSyncMode = SyncMode.SyncPerWord;
        sc.Modules[2].ClockPeriod = 3;
        sc.Modules[2].PostDelay = 0;
        sc.Modules[2].PreDelay = 0;
        sc.Modules[2].FrameDelay = 7;
        client.Sfio.Spi.SetConfig( sc );

        // Define the IPG Super Mode configuration we want to use.
        // TODO: put some genuinely useful value here!
        uint[] unlockCmds = new uint[] {
            ( (uint)ConfigFlags.Write_Access | (uint)( Register.Unlock ) | ( (uint)ConfigFlags.Data_Mask & (uint)UnlockCode.First ) ),
            ( (uint)ConfigFlags.Write_Access | (uint)( Register.Unlock ) | ( (uint)ConfigFlags.Data_Mask & (uint)UnlockCode.Second ) )
        };

        // Send the configuration via the SPI.
        uint[] spiResponse = client.Sfio.Spi.Transceive( 2, unlockCmds, 10 );
        // Check the response(s).
        if ( spiResponse[1] != 3 )
        {
            throw new Exception( "SPI Unlock sequence failed." );
        }

        // Define the alarm matrix for our application.
        UInt64 alarmMatrix = 0x0001001000001100;

        uint[] alarmMatrixCmds = new uint[] {
            ( (uint)ConfigFlags.Write_Access | (uint)( Register.AlarmMatrix0 ) | ( (uint)ConfigFlags.Data_Mask & (uint) (alarmMatrix >> 0 ) )),
            ( (uint)ConfigFlags.Write_Access | (uint)( Register.AlarmMatrix1 ) | ( (uint)ConfigFlags.Data_Mask & (uint) (alarmMatrix >> 16) )),
            ( (uint)ConfigFlags.Write_Access | (uint)( Register.AlarmMatrix2 ) | ( (uint)ConfigFlags.Data_Mask & (uint) (alarmMatrix >> 32) )),
            ( (uint)ConfigFlags.Write_Access | (uint)( Register.AlarmMatrix3 ) | ( (uint)ConfigFlags.Data_Mask & (uint) (alarmMatrix >> 48) ))
        };

        // Send the configuration via the SPI.
        client.Sfio.Spi.Transmit( 2, alarmMatrixCmds, false );
    }
    catch ( Exception ex )
    {
        Console.WriteLine( "Uhhh, Houston? We've had a problem...{0}", ex.ToString() );
    }
}